1. Field of the Invention
The present invention relates to a liquid crystal display device including a pixel memory provided in each of LCD pixels to store an image data, and especially to control voltages applied to a pair of electrodes of respective pixels arranged in the liquid crystal display device.
2. Description of the Background Art
Liquid crystal display devices are widely used as typical display devices for various kinds of equipments such as personal computers, OA equipments, and TV sets because the display devices have many advantages such as lightness, compactness and low power consumption. In recent years, mobile liquid crystal display devices find use in mobile terminal equipments such as a mobile phone, a car navigation device and a game player, and a large size display panel has been in need. In order to meet such need, compactness, low power consumption or long time battery use have been requested.
A liquid crystal display device with a pixel memory in the LCD pixel is well-known as a display device to achieve low power consumption. In this type liquid crystal display device, a refresh operation is not required when a static image is displayed because a static memory is embedded in each pixel. Accordingly, power consumed by data lines or data driving circuits may be fully cut as shown, for example, in Japanese Patent Application 2007-199441.
FIG. 12 of the Japanese Patent Application illustrates a circuit diagram, in which a drain electrode of a first transistor 15 is connected to an input terminal a1 to set a memory state of the static memory. A drain electrode of a second transistor 18 is connected to the input terminal az1 to reset the memory state, and a source electrode of the first transistor 15 is connected to a data line S1. Gate electrodes of the first and second transistors formed in the pixels arranged in parallel with gate lines are connected to corresponding gate lines, respectively. In the pixels arranged in a row direction, for example, the gate electrodes of the first and second transistors 15 and 18 are connected to a pair of gate lines G1 and G0, respectively.
The circuit diagram shown in FIG. 12 has following problems. The voltages VLCa and VLCb are periodically inverted. Since the voltages VLCa and VLCb are connected to a total liquid crystal capacitance of all the pixels in the display area, it is necessary to design driving circuits such as output buffers for voltages VLCa and VLCb so that a driving ability of output buffers is sufficiently high to enable voltages applied to the liquid crystal capacitance of all pixels invert simultaneously, which results in an increase in power consumption of the driver circuits.
Furthermore, when the driving circuits for the voltages VLCa and VLCb are formed in the array substrate using the same process as the pixels, the circuit size of the driving circuits becomes large and a large layout space is required, which may result in an enlargement of a frame size and further a lowering of a product value.
Moreover, the voltages VLCa and VLCb are supplied to the liquid crystal capacitance through N channel type transistors. In such a case, if a gate voltage VDD to make the N channel transistor conductive is the same level as that of high level “H” of the voltages VLCa and VLCb, a voltage level reduced by the threshold voltage Vth of the N channel type transistor from the “H” level is applied to the liquid crystal capacitance. Therefore, a decreased contrast or a flicker phenomenon may occur due to a voltage shift between a pixel voltage and a common voltage supplied to the liquid crystal layer.
In a moving image display, it is necessary to store different signals successively in the pixels while driving the liquid crystal layer by AC operation in the Japanese Application. Accordingly, an inversion operation of a polarity of voltage to maintain pixel signals is required, that is, a polarity of a data signal is inverted corresponding to inversion of a polarity of the frame (common voltage). Otherwise, power consumption of a driver circuit for data lines may be increased.
Moreover, in this technology, a problem is noted that a current to maintain a pixel signal is not easily discharged when a power becomes on or off and an abrupt power failure occurred, which may result in generation of a display time lag.